Fabricating a semiconductor device that includes integrated circuits on a semiconductor wafer is a multi-step process. For instance, to form a redistribution layer (“RDL”) on the semiconductor wafer, a dielectric layer is formed on an active surface of the semiconductor wafer, which also includes bond pads. A metal from which traces or redistribution lines of the RDL are to be formed is then blanket-deposited on the unpatterned dielectric layer. A photoresist layer is applied over the metal layer and patterned using conventional photolithographic techniques to form an etch mask for defining the traces. However, to form the etch mask, a stepper is needed to create line definitions in the photoresist layer by selective exposure thereof. The pattern in the photoresist layer is transferred to the metal layer using a wet etch process, forming the metal traces. The metal traces of the RDL are used to reroute original bond pad locations on, for example, a centerline or periphery of a semiconductor device to an array format, whereon solder bumps or other conductive elements for external connection of the semiconductor device may be applied or formed.
However, so-called “etch bias” is a problem with this process due to the substantially isotropic nature of the wet etch used to pattern the metal underlying the photoresist layer. The wet etch causes undercutting of the metal layer, which leads to the metal trace being smaller in width than the width of the corresponding pattern in the etch mask. The observed undercut is approximately the same for wide metal traces and narrow metal traces, which limits the size of the metal trace for a given thickness of the metal layer. With the decreasing size of features that are formed on semiconductor devices, etching must be accurate and feature dimensions maintained within very precise tolerances to preserve the alignment of, and optimize the electrical characteristics of, small features. However, the necessary degree of precision is not achieved with most conventional wet etch processes. As such, wet etch processes are typically used to faun larger features, such as those exhibiting dimensions above 3 μm. Therefore, as feature sizes on state-of-the-art semiconductor devices continue to decrease, the usefulness of wet etch processes becomes limited.
To reduce the undercutting of the metal layer, a dry etch process can be used during RDL fabrication. Since dry etch processes removal material substantially anisotropically, the dry etch is capable of accurately reproducing the features of the etch mask over the metal layer. However, most dry etch processes lack the etch specificity that is possessed by many wet etch processes. For instance, if a plasma etch is used, portions of photoresist ash resulting from use of this process attack the dielectric layer, producing an undesirable undercut of the dielectric layer. A dry etch process is also less desirable because the dry etch process is more complicated and expensive than a wet etch process.
To overcome these deficiencies, it would be desirable to be able to form a small feature metal pattern, such as metal traces of an RDL, using a wet etch process. In addition to extending the end-of-life expectation for wet etch capability as feature sizes continue to shrink, the dimensions of the resulting metal pattern are substantially similar to the dimensions of the pattern in the etch mask.